This invention relates to static analysis of circuits.
Computer-aided design (CAD) and electronic design automation (EDA) tools have been applied to design of integrated circuits. One aspects of such tools relates to analysis of circuits to predict characteristics such as timing and power consumption. For example, given a circuit of interconnected gates, and fabrication characteristics of the gates and the interconnects, tools are available today that predict timing characteristics including delay characteristics through different parts of the circuit. These timing characteristics can be used to identify critical timing paths, for example, that may limit the achievable clocking speed of the circuit. Commercial tools for integrated circuit design are available from vendors including Synopsys, Inc., and Cadence Design Systems, Inc.
Computational requirements of design tools generally increase as the number of elements in circuits grow, and as the complexity of the analysis being performed increases. For example, timing analysis can be performed using a statistical framework rather than relying on best-case and worst-case limits but such statistical analysis requires more computation. Also, as circuits become more complex, more iterations of circuit refinement may be needed, further increasing the computational requirements. Some analysis makes use of iterative computations, for example, in order to determine signal integrity characteristics of a circuit, which relate to interaction between signals on different signal lines. As circuits become more complex, such iterative techniques can result in computation times that grow faster than the growth in the size of the circuits being analyzed.
With today's analysis tools, parallel processing approaches using multiple computers and/or multiple processors in a single computer running separate processing threads do not, in general, themselves provide the computational speedups required to compensate for the increased computation requirements. For example, bottlenecks such as memory access can remain, and iterative techniques and repeated analysis after circuit modifications can outstrip available gains through parallel processing.
During a circuit design and refinement process using currently available tools, analysis is generally begun anew after each circuit modification. This approach further increases computation costs as more circuit refinements are needed for complex circuits.